Tag: #risc-v
Writing on GPUs, LLMs, MLOps, Kubernetes — and mindset · 6 posts
6 posts are tagged #risc-v; the most recent was published on 2026-07-16.
Often tagged together: #deep-dive 3 #english 3 #cache 2 #computer-architecture 2 #cpu 2
Most read in the last 90 days:
- Open Hardware & Maker Tech 2026 — Framework / Raspberry Pi 5 / Pico 2 RP2350 / Arduino R4 / ESP32 / M5Stack / Jetson Deep Dive
- Open FPGA & RISC-V Development 2026 Deep Dive - Yosys, NextPnR, IceStorm, Lattice ECP5, SiFive, BeagleV-Fire, Tang Nano, PULPino
- The RISC-V RVA23 Profile — Distros Raised the Baseline, the Hardware Has Not Arrived Yet
The RISC-V RVA23 Profile — Distros Raised the Baseline, the Hardware Has Not Arrived Yet
RVA23 is the RISC-V application-processor profile ratified on October 21, 2024, and it is the first to make the Vector extension (V) and the Hypervisor extension (H) — both optional under RVA22 — mandatory. This matters
2026-07-16 · 17 min read #risc-v#rva23#ubuntu#toolchain#cpu-architectureOpen FPGA & RISC-V Development 2026 Deep Dive - Yosys, NextPnR, IceStorm, Lattice ECP5, SiFive, BeagleV-Fire, Tang Nano, PULPino ♪ Listenable
A 2026 landscape of open FPGA and RISC-V development. With Yosys + NextPnR + IceStorm / Project Trellis / Apicula you can synthesize and place-and-route iCE40, ECP5 and Gowin parts with a fully open toolchain. This guide
2026-05-16 · 35 min read #english#fpga#risc-v#yosys#nextpnrOpen Hardware & Maker Tech 2026 — Framework / Raspberry Pi 5 / Pico 2 RP2350 / Arduino R4 / ESP32 / M5Stack / Jetson Deep Dive ♪ Listenable
A complete tour of the 2026 open hardware and maker ecosystem — Framework finishing a Series B with modular laptops, Raspberry Pi completing the lineup with Pi 5 / Pi 500 / Pi AI Kit, the Pico 2 introducing a dual Arm /
2026-05-16 · 35 min read #open-hardware#maker#framework-laptop#raspberry-pi-5#pi-500Hardware HDL & Chip Design 2026 — SystemVerilog / Chisel / SpinalHDL / Amaranth / Yosys / Verilator / TinyTapeout / OpenROAD Deep Dive ♪ Listenable
The hardware description language (HDL) and chip-design landscape in 2026 is multi-layered. The industry standard is still Verilog/SystemVerilog, but UC Berkeleys Chisel has become the de facto choice for RISC-V cores li
2026-05-16 · 24 min read #hdl#hardware-design#chip-design#verilog#systemverilogModern Computer Architecture — CPU Pipelines, Out-of-Order, Caches, Branch Prediction, Meltdown, Apple Silicon, ARM, RISC-V, SIMD, GPU Deep Dive (2025)
Why arrays beat linked lists, why a branch can be 10x slower, how M1 beat Intel. CPU pipelines, Out-of-Order, L1 to L3 caches, branch prediction, Meltdown/Spectre, Apple Silicon, ARM/x86/RISC-V, SIMD, GPU SM/Warp, HBM/CX
2026-04-15 · 15 min read #computer-architecture#cpu#cache#branch-prediction#apple-siliconComputer Architecture Complete Guide: From ISA to GPU Parallel Architecture ♪ Listenable
A comprehensive guide to computer architecture covering ISA, datapath, pipelining, cache memory, virtual memory, RISC-V, and GPU parallel architecture with code examples.
2026-03-17 · 23 min read #computer-architecture#cpu#gpu#pipeline#cache