Tag: #chip-design
Writing on GPUs, LLMs, MLOps, Kubernetes — and mindset · 2 posts
Hardware HDL & Chip Design 2026 — SystemVerilog / Chisel / SpinalHDL / Amaranth / Yosys / Verilator / TinyTapeout / OpenROAD Deep Dive ♪ Listenable
The hardware description language (HDL) and chip-design landscape in 2026 is multi-layered. The industry standard is still Verilog/SystemVerilog, but UC Berkeleys Chisel has become the de facto choice for RISC-V cores li
2026-05-16 · 24 min read #hdl#hardware-design#chip-design#verilog#systemverilogAI Hardware EDA & Chip Design 2026 Complete Guide — Cadence Cerebrus + JedAI · Synopsys DSO.ai + AgentEngineer · Siemens Calibre AI · ANSYS PathFinder · NVIDIA ChipNeMo · Google AlphaChip · OpenROAD Deep Dive ♪ Listenable
In 2026 the chip industry sits at the intersection of two curves. On one side, the 2nm GAA (Gate-All-Around) node is finally in mass production — TSMC N2, Samsung SF2, Intel 18A, and Rapidus 2nm all brought up shipping l
2026-05-16 · 23 min read #ai-eda#chip-design#cadence-cerebrus#synopsys-dso-ai#siemens-calibre