Quiet the echo with one resistor
In one line
Series termination absorbs the wave returning to the source, and parallel termination reduces reflection at the load. Even if the number 50Ω appears in both, the circuit's voltages and supply current are not the same.
Why this was needed
When you see a reflection, it is easy to think, "I'll just put in a 50Ω resistor". But if you leave out where to put it and how much resistance the driver already has, you build a circuit different from what you intended. In real design reviews too, the value and the location are a pair. In this module, you keep the other parts as they are and change only the termination location to isolate the cause.
The first received voltage of the reference circuit was about 5.5V. One way to bring this result down to 3.3V is to match the source's total resistance to the line. But "we reduced the high voltage" alone does not finish every design problem. With a different line impedance, driver resistance, load, or receiving time, the remaining error differs.
How it works
Look again at the source reflection coefficient ΓS=(Rs−Z0)/(Rs+Z0). If Rs=Z0, the numerator is 0, so the wave returning to the source is not reflected again toward the load. This driver is already 10Ω, so the added series resistance is 40Ω. If you set the added resistance to 50Ω, the total is 60Ω and does not match the nominal line's 50Ω.
If you match the source, the voltage that first goes out onto the line is half the supply, that is, 1.65V. At a very large load the reflected wave adds, and the receiving end becomes about 3.3V. So you must not judge "it's a failure because only half goes out" by looking only at the first waveform at the transmitting end. Where and when you read it is part of the result.
When the wave returning from the load arrives at the source, the transmitting-end voltage itself can change. ΓS=0 does not mean the voltage of that node is forever its first value; it means the arriving wave does not bounce forward again. If you distinguish a real circuit's node voltage from the component of a wave traveling in one direction, this apparent contradiction is resolved.
Conversely, if you make the load resistance RL equal to 50Ω, same as Z0, then ΓL=0. Then no wave returns from the load. Suppose the added series resistance is 0Ω and the driver stays at 10Ω. The wave that first goes out onto the line is 3.3×50/(10+50)=2.75V and the receiving end is also 2.75V. You eliminated the reflection, but the logic voltage did not become equal to the supply.
| Experiment | Added series resistance | Load | What to compare first |
|---|---|---|---|
| Reference | 0Ω | 1GΩ | The first received overshoot and the later reflections |
| Series termination | 40Ω | 1GΩ | Total source 50Ω and the first received voltage |
| Parallel termination | 0Ω | 50Ω | The drop in received voltage and the continuous current |
Parallel termination also has another cost, power. In the long-settled DC state of an ideal lossless line, you can calculate the current with the source and load resistors. Current I=Vs/(Rs+RL), and load power P=I²RL. This value is a steady-state prediction, not an instantaneous power measured at an arbitrary point within the first 14ns.
For example, with Vs=3.3V, Rs=10Ω, and RL=50Ω, I=0.055A and the load power is 0.15125W. If you want to show it in mA, multiply by 1,000 at the end. The returned fields of the analysis function are current_a and load_w, so putting 55 as is into current_a is a 1,000-fold error. You must also guard against the case where the voltage and resistance calculations are right but the result is wrong in the unit conversion.
Even so, you cannot say that this calculation has chosen the rating of a real resistor. Temperature, duty ratio, the driver's nonlinear output resistance, and real protection conditions are missing. What we compare is the difference the termination method makes in the stated ideal model. The checklist needed when applying it to a product is kept separately from the calculation of this small model.
Is the 40Ω matched at the nominal values perfect under all conditions? If you change the driver to 8/10/12Ω and the line to 45/50/55Ω, there are 9 combinations in total. The added resistance stays fixed at 40Ω. If you reoptimize the added resistance for every combination, you end up comparing different designs instead of asking "how much deviation does one and the same part tolerate".
If you gather the received maxima of the 9 waveforms, you can find residual reflections that were not visible in a single representative condition. This grid is an educational set of conditions and not the probability distribution of a process. If one out of nine showed a high value, you cannot estimate that one ninth of production units fail. To talk about probability, you need other evidence such as distributions and correlations.
The analysis function summarize returns count, min_peak_v, max_peak_v, and max_case. If the highest values are the same, pick the combination whose name comes first in dictionary order. This rule is not a law of physics but a convention for the reproducibility of the report. That is because if the name of the highest condition changed just because the order in which the directory was read changed, it would be hard to compare each other's results.
What it looks like in the field
If you change several conditions at once, it is hard to know the cause even when the result improves. First keep the reference circuit, and generate series and parallel each in a separate folder. The folder must link the input model, the circuit text, the waveform, and the run report. If you keep overwriting "final.csv", you rely on memory in the meeting for which resistor you used.
The practical work of extracting Z0 from a driver model and a PCB stackup is not in this course. Here you practice the feel of automatically reading results while iterating over a provided set of numbers. Later, when you attach real part models, frequency-dependent loss, and measurement results, this working habit of linking conditions and output files is still needed.
What to learn next
In the next module you see why you must reverify the result even though the solver succeeded. In the last lab, you create separate output folders for series termination and parallel termination and also calculate the numerical difference by halving the time step. We will distinguish a claim that one maximum got smaller from a verification report that connects the evidence.