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• Trust the System, Not Yourself — The Secret to Not Making Mistakes ♪ Listenable

  Human memory and willpower are far more fragile than we like to admit. What prevents mistakes is not stronger willpower but a well-designed system. This is about building structures of checklists, automation, and externa

  2026-06-17 · 23 min read #system#checklist#automation#productivity#mindset

• Metacognition and Strengthening the Circuit — Retrieval Builds the Brain

  Listening alone does not build the circuit. Only when you retrieve does the circuit fire and grow stronger. This essay covers the science of retrieval practice, using metacognition to discover what you do not know, and m

  2026-06-17 · 17 min read #metacognition#retrieval-practice#learning#language#memory

• When Times Are Hard, Imagine the Worst and Separate Your Emotions ♪ Listenable

  The Stoics deliberately trained negative visualization — picturing the worst in advance. Imagining a deeper bottom when times are hard lets you endure the present, and separating emotion from fact reduces the wobble. But

  2026-06-17 · 20 min read #stoicism#resilience#emotional-regulation#self-improvement#mindset

• FingerScore Hardware 3 — MCU Firmware and Gesture Input Processing

  This post covers the brain of the FingerScore BLE ring device for racket-sports score keeping: the MCU firmware. From the structure of init, main loop, interrupts, and low-power sleep, through detecting buttons and gestu

  2026-06-17 · 17 min read #fingerscore#firmware#mcu#embedded#gesture

• FingerScore Hardware 4 — Designing BLE Wireless Communication (From GATT to Mobile Integration)

  We design the BLE wireless communication at the heart of the FingerScore smart-scoring ring from the ground up. GAP/GATT concepts, a custom score service, pairing security, Web Bluetooth and Android integration, power sa

  2026-06-17 · 15 min read #fingerscore#ble#bluetooth#gatt#embedded

• FingerScore Hardware 6 — PCB Design and Miniaturization (Building It Into a Ring)

  We cover the final step that turns the FingerScore circuit into a real, touchable ring: PCB design. The schematic-to-PCB flow, component placement and routing, ring form-factor constraints, 2.4GHz antenna layout, DFM and

  2026-06-17 · 15 min read #fingerscore#pcb#kicad#antenna#miniaturization

• FingerScore Hardware 2 — Electronics Fundamentals (From Voltage, Current, and Resistance to Digital Signals) ♪ Listenable

  Everything you need from electronics fundamentals to build the FingerScore ring device, in one piece. We walk through Ohm law and voltage dividers, pull-up and pull-down resistors, capacitors, LED current-limiting calcul

  2026-06-17 · 23 min read #fingerscore#electronics#hardware#gpio#i2c

• FingerScore Hardware 5 — Power, Battery, and Circuit Design

  We cover, from scratch, the power design that actually keeps the FingerScore ring on. A power budget calculation, coin cell vs. LiPo, charging ICs and protection circuits, LDOs and buck converters, decoupling, low-power

  2026-06-17 · 16 min read #fingerscore#power#battery#lipo#circuit

• Building FingerScore Hardware 1 — System Design and Bill of Materials (BOM) ♪ Listenable

  This is part one of a hardware series on building the FingerScore ring-shaped score recorder yourself. It walks through translating product requirements into circuits, the system block diagram from sensor to MCU to radio

  2026-06-17 · 29 min read #fingerscore#hardware#electronics#ble#embedded

• Why ripgrep Is So Fast

  ripgrep beats grep not through magic but through an accumulation of decisions: the Rust regex crate built on finite automata (no backtracking), SIMD-accelerated memchr, parallel directory traversal, respecting .gitignore

  2026-06-17 · 12 min read #rust#performance#tools#cli

• Systolic Arrays and Dataflow Architecture — The Heart of the TPU ♪ Listenable

  A deep dive into the systolic array, the structure that lets AI accelerators run matrix multiplication efficiently, complete with ASCII diagrams. We walk through dataflow strategies like weight-stationary and output-stat

  2026-06-16 · 20 min read #gpu-cuda#systolic-array#dataflow#tpu#ai-hardware

• Making Inference Fast — Quantization, Sparsity, and Dataflow from a Hardware Lens ♪ Listenable

  We break down the cost structure of inference through the memory-wall lens, then connect quantization (INT8/FP8/FP4), structured sparsity (2:4), dataflow architectures, operator fusion, batching and KV caching into one p

  2026-06-16 · 18 min read #inference#quantization#sparsity#dataflow#gpu

• GPU vs TPU vs ASIC — The 2026 Inference War ♪ Listenable

  A comparison of the GPU, TPU, and ASIC competition over 2026 inference workloads. We cover Google TPU v6 Trillium and Ironwood, the fast-growing cloud in-house inference ASICs, the throughput/latency/cost/power trade-off

  2026-06-16 · 23 min read #gpu#tpu#asic#inference#ai-hardware

• Cerebras Wafer-Scale Deep Dive — A Whole Model on a Single Chip ♪ Listenable

  A close look at the design of the Cerebras WSE-3, a single chip carved from an entire wafer. We cover the on-chip SRAM-centric structure that routes around the memory wall, the fault-tolerant design, real-time inference

  2026-06-16 · 20 min read #cerebras#wafer-scale#ai-hardware#memory-wall#inference

• Power and Cooling in the AI Data Center — Infrastructure for the Gigawatt Era ♪ Listenable

  As AI capex explodes and data centers grow to gigawatt scale, power and cooling have emerged as the dominant constraints. We map the big picture: surging rack power density, the limits of air cooling versus direct liquid

  2026-06-16 · 21 min read #datacenter#ai-infrastructure#cooling#power#liquid-cooling

• The Memory Wall and HBM — The Real Bottleneck That Divides AI Performance ♪ Listenable

  In an era where compute is cheap and data movement is expensive, the real bottleneck of AI performance is memory. From the memory-wall concept to HBM generations, the roofline model and arithmetic intensity, the KV cache

  2026-06-16 · 21 min read #memory-wall#hbm#bandwidth#roofline#inference

• Groq and SambaNova — Chips That Went All In on Inference ♪ Listenable

  A deep look at the working principles of two chips that bet everything on inference rather than training: the Groq LPU and the SambaNova RDU. We cover how deterministic execution and compiler scheduling, plus reconfigura

  2026-06-16 · 19 min read #groq#sambanova#inference#ai-hardware#lpu

• Chiplets and Advanced Packaging — CoWoS, 3D Stacking, and Beyond Moore ♪ Listenable

  A single giant die can no longer push performance higher on its own. This post walks through how chiplets, CoWoS, 3D stacking, and the UCIe standard turned advanced packaging into the variable that decides accelerator pe

  2026-06-16 · 27 min read #gpu-cuda#chiplet#advanced-packaging#cowos#ucie

• AI Interconnect — NVLink, NVSwitch, UALink, and the Art of Scaling Up ♪ Listenable

  In large-scale AI training and inference, the real bottleneck is not compute but communication. This article walks through the principles and practice of AI interconnect — the scale-up domains built by NVLink and NVSwitc

  2026-06-16 · 29 min read #gpu-cuda#nvlink#nvswitch#ualink#interconnect

• Photonic Computing and Optical Interconnects — Crossing the Memory Wall with Light ♪ Listenable

  In 2026, electrical interconnects have hit the wall of the memory wall and data-movement energy. This post explains how silicon photonics and optical interconnects aim to cross that wall — covering Lightmatter Passage, D

  2026-06-16 · 25 min read #gpu-cuda#photonics#silicon-photonics#optical-interconnect#co-packaged-optics