Tag: #ai-hardware

← All posts

• Systolic Arrays and Dataflow Architecture — The Heart of the TPU ♪ Listenable

  A deep dive into the systolic array, the structure that lets AI accelerators run matrix multiplication efficiently, complete with ASCII diagrams. We walk through dataflow strategies like weight-stationary and output-stat

  2026-06-16 · 20 min read #gpu-cuda#systolic-array#dataflow#tpu#ai-hardware

• GPU vs TPU vs ASIC — The 2026 Inference War ♪ Listenable

  A comparison of the GPU, TPU, and ASIC competition over 2026 inference workloads. We cover Google TPU v6 Trillium and Ironwood, the fast-growing cloud in-house inference ASICs, the throughput/latency/cost/power trade-off

  2026-06-16 · 23 min read #gpu#tpu#asic#inference#ai-hardware

• Cerebras Wafer-Scale Deep Dive — A Whole Model on a Single Chip ♪ Listenable

  A close look at the design of the Cerebras WSE-3, a single chip carved from an entire wafer. We cover the on-chip SRAM-centric structure that routes around the memory wall, the fault-tolerant design, real-time inference

  2026-06-16 · 20 min read #cerebras#wafer-scale#ai-hardware#memory-wall#inference

• The Memory Wall and HBM — The Real Bottleneck That Divides AI Performance ♪ Listenable

  In an era where compute is cheap and data movement is expensive, the real bottleneck of AI performance is memory. From the memory-wall concept to HBM generations, the roofline model and arithmetic intensity, the KV cache

  2026-06-16 · 21 min read #memory-wall#hbm#bandwidth#roofline#inference

• Groq and SambaNova — Chips That Went All In on Inference ♪ Listenable

  A deep look at the working principles of two chips that bet everything on inference rather than training: the Groq LPU and the SambaNova RDU. We cover how deterministic execution and compiler scheduling, plus reconfigura

  2026-06-16 · 19 min read #groq#sambanova#inference#ai-hardware#lpu

• AI Interconnect — NVLink, NVSwitch, UALink, and the Art of Scaling Up ♪ Listenable

  In large-scale AI training and inference, the real bottleneck is not compute but communication. This article walks through the principles and practice of AI interconnect — the scale-up domains built by NVLink and NVSwitc

  2026-06-16 · 29 min read #gpu-cuda#nvlink#nvswitch#ualink#interconnect

• Photonic Computing and Optical Interconnects — Crossing the Memory Wall with Light ♪ Listenable

  In 2026, electrical interconnects have hit the wall of the memory wall and data-movement energy. This post explains how silicon photonics and optical interconnects aim to cross that wall — covering Lightmatter Passage, D

  2026-06-16 · 25 min read #gpu-cuda#photonics#silicon-photonics#optical-interconnect#co-packaged-optics

• In-Memory Computing Principles — Computing Inside the Memory ♪ Listenable

  A deep look at the principles of compute-in-memory (CIM): computing directly inside memory instead of moving data to a compute unit. We cover solving a matrix multiply in one shot with a crossbar array, the difference be

  2026-06-16 · 19 min read #in-memory-computing#compute-in-memory#ai-hardware#crossbar#reram

• The AI Semiconductor Supply Chain and Market — Who Actually Makes the Chips (2026) ♪ Listenable

  We trace the value chain behind a single AI chip — design, EDA, IP, foundry, packaging, HBM, and equipment. From TSMC and Samsung to ASML EUV, the CoWoS bottleneck, geopolitics and export controls, the rise of in-house c

  2026-06-16 · 19 min read #gpu-cuda#ai-hardware#semiconductor#supply-chain#tsmc

• The 2026 AI Accelerator Landscape — From Blackwell to Vera Rubin ♪ Listenable

  A developer-oriented map of the 2026 AI accelerator market. We cover NVIDIA Blackwell and the next-generation Vera Rubin, AMD MI350X, the moment inference capex first overtook training, and how to choose a chip per workl

  2026-06-16 · 21 min read #ai-hardware#nvidia-blackwell#vera-rubin#inference#gpu

• AI Hardware Research Trends 2026 — The Future Through the Papers ♪ Listenable

  A field-by-field review of where AI hardware research is heading in 2026. From wafer-scale and photonics, compute-in-memory, FP4 low-precision training, sparsity and MoE hardware, optical interconnect, next-generation me

  2026-06-16 · 19 min read #ai-papers#ai-hardware#photonics#compute-in-memory#low-precision

• AI Hardware Accelerators 2026 — NVIDIA Blackwell / AMD Instinct MI400 / Google TPU Trillium / Cerebras WSE-3 / Groq LPU / Tenstorrent / Etched Sohu / Furiosa / Rebellions Deep Dive ♪ Listenable

  In 2026 AI hardware is no longer an NVIDIA-only story. Blackwell (B100/B200/GB200 NVL72/B300) landed at GTC 2024, Rubin is queued for September 2026, AMD Instinct has marched from MI300X through MI355X to MI400 Helios, I

  2026-05-16 · 20 min read #ai-hardware#gpu#accelerator#nvidia-blackwell#b100

• AI Supercomputer at Home: Study LLMs on NVIDIA DGX Spark and Create Content with ComfyUI ♪ Listenable

  Run 200B-parameter LLMs locally on NVIDIA DGX Spark ($3,999) and generate FLUX/SDXL images with ComfyUI. Complete guide with specs, benchmarks, setup instructions, and cost analysis — the era of personal AI supercomputer

  2026-03-21 · 37 min read #nvidia#dgx-spark#comfyui#local-ai#llm

• Google TPU Deep Dive: How Systolic Arrays Solve Matrix Multiplication Perfectly

  A complete technical breakdown of how Google's Systolic Array achieves extreme efficiency for matrix multiplication. From INT8 inference and bfloat16, to XLA compiler optimizations and TPU Pod distributed inference - wit

  2026-03-18 · 15 min read #tpu#google#systolic-array#model-serving#jax

• NPU Deep Dive: How Transformer Architecture Runs Directly on Silicon ♪ Listenable

  A complete technical breakdown of how NPUs differ from CPUs and GPUs, how every transformer operation maps to hardware, and why LLM inference is memory-bound — not compute-bound. From Apple ANE to Qualcomm Hexagon, Groq

  2026-03-18 · 22 min read #npu#transformer#ai-hardware#quantization#kv-cache

• AI Hardware Accelerators Complete Guide: H100, TPU, Cerebras, and Edge AI Chips Compared

  A comprehensive comparison guide covering NVIDIA H100 Tensor Core, Google TPU v5 systolic array, Cerebras WSE-3, AWS Inferentia 2, and Apple Neural Engine for AI hardware accelerators.

  2026-03-17 · 17 min read #ai-hardware#h100#tpu#cerebras#edge-ai

• The Peak of the AI Memory Supercycle: 5 Decisive Moments for HBM That Will Shake the 2026 Semiconductor Market ♪ Listenable

  From HBM4 16-layer stacking technology, the emergence of custom HBM (cHBM), the strategic clash between SK Hynix, Samsung, and Micron, to the memory supercycle market outlook and HBM vs GDDR comparison — an in-depth anal

  2026-03-01 · 37 min read #hbm#semiconductor#memory#ai-hardware#sk-hynix