Why Second-Order Filters Can Behave Differently

In one line

A filter having two stages does not make it the same second-order response. You can choose a design only by distinguishing the connection loading from the pole placement and checking the frequency response and the step response together.

Why this was needed

In the previous unit you concluded that there is no single RC that reduces the greenhouse fan's 875Hz interference while preserving the 125Hz signal. Now three proposals come up in the design meeting. Add one more of the same RC, put a buffer in between, or use an entirely different second-order filter. All use two capacitors, so will the results be the same too?

Instead of creating a success number by changing the conditions, we will check how the circuit structure changes the transfer function. We keep the existing requirement that the desired 125Hz gain is 0.9 or more and the interfering 875Hz gain is 0.1 or less. To this we add time requirements: overshoot of a 1V step input ≤0.05V and an observed 2% settling time ≤10ms. That is because a sensor that reacts too strongly to a normal abrupt change is hard to adopt on the basis of two frequency points alone.

This experiment uses ideal linear filters. The buffer is an ngspice controlled voltage source and does not have the bandwidth, supply, output limit, or slew rate of a real operational amplifier. We do not extend the circuit chosen in this step into a part-value recommendation or an operating guarantee for a real circuit.

How it works

The numbers of an AC analysis are not a time waveform

An AC analysis finds the complex input and output voltages at each frequency. The real part and the imaginary part are not values of different sensors but two components expressing the magnitude and phase of one voltage. After first computing the transfer function H=Vout/Vin, the gain is |H|, the voltage gain in dB is 20log10|H|, and the phase is atan2(Im H,Re H) converted to degrees.

The ngspice control language tutorial shows the format in which a complex vector is recorded as real-part and imaginary-part columns in AC output. This file has five columns: frequency, input real part, input imaginary part, output real part, and output imaginary part. That v(in) and v(out) each appear twice in the header is not a duplication error.

The provided input has AC amplitudes of 0.5, 1, and 2V and a phase of 23 degrees. If you do not divide out the input, changing the amplitude changes the gain too, and the input's phase gets mixed into the filter phase. To avoid an implementation whose output magnitude happens to be right only for a 1V input, other amplitudes are also checked. 10log10 is not the formula to apply to a voltage ratio here. Also, if you use only atan(Im/Re), you lose the quadrant in intervals where the real part is negative.

The observation is 241 points from 10Hz to 10kHz at 80 intervals per decade. 125Hz and 875Hz are included exactly in a separate small linear observation. You do not replace the required frequency with the nearest point of a log sweep. If the output is exactly 0, the gain is 0 but the log and the phase are not meaningful finite numbers, so they are left as null in the report.

The new term that arises when you attach two RCs

Set R=1kΩ, C=1/(2πRf₀), and p=jf/f₀. One RC is H=1/(1+p). Two of the same RC separated by an ideal buffer are H=1/(1+p)², and expanding the denominator gives 1+2p+p². Because each stage does not see the load of the other, the two transfer functions can be multiplied.

If you connect them directly without a buffer, the second R and C become the load of the first output. If you set the intermediate node voltage separately and write the sum of currents, you get H=1/(1+3p+p²). The added p term changes the attenuation and the time response. Analog Devices' cascaded RC experiment also explains that because of this loading effect, the simple product of the individual responses can differ from the real connection.

At f=f₀, the gains of the three circuits are 1/√2, 1/2, and 1/3 respectively. The latter two are both second order and their phase at this frequency is also −90 degrees, but their amplitudes are not the same. The order alone cannot determine the shape of the passband or the rate of attenuation at every frequency. You must distinguish the slope approached at high frequencies from the actual value in the transition band.

Sallen–Key chooses not only the order but also Q

This unity-gain Sallen–Key connects R1 from the input to the intermediate node, R2 from that node to the buffer input, C1 from the intermediate node to the buffer output, and C2 from the buffer input to ground. The buffer is an ideal model that reads the input and passes it to the output as is. Setting R1=R2=R, C1=2QC, and C2=C/(2Q) gives H=1/(1+p/Q+p²).

When Q=1/√2, it is the second-order Butterworth response. Analog Devices' explanation of phase response covers how the shape and phase shift of a second-order response change with Q. It also distinguishes the response of two identical first-order filters in series so that it is not confused with the second-order Butterworth. In this course you compare them with circuit files at the same f₀.

Here f₀ does not mean the −3dB frequency of every circuit. For rc1 and the second-order Butterworth that meaning holds, but it cannot be applied as is to another Q or to an RC with loading. That is why the configuration field is f0_hz, not cutoff_hz. If you distinguish them from the name, you reduce attaching a wrong physical meaning in the report.

The representative values to calculate directly at f₀=220Hz and check against the simulation are as follows. The next lab requires not a function that returns the table as is but a function that reads real files.

Circuit	125Hz gain	875Hz gain	1V step overshoot
One RC	About 0.869	About 0.244	About 0V
Two RCs, direct connection	About 0.545	About 0.053	About 0V
Two RCs, ideal buffer	About 0.756	About 0.059	About 0V
Sallen–Key, Q=1/√2	About 0.952	About 0.063	About 0.043V
Sallen–Key, Q=1.4	About 1.267	About 0.066	About 0.301V

With a high Q, the gain at the desired frequency becomes greater than 1. Since this AC requirement sets only a minimum value, you can let it pass if you look only at the two frequency conditions. But it is eliminated by the 5% overshoot limit of the step input. This is not an exception that cheats the test but a case showing what was missing from the requirement list. If flatness or an upper gain limit matters, that too must be declared as a separate requirement.

Entering the band for the first time is not settling

The input is 0V until 1ms, then rises to 1V over the next 1µs and holds until 50ms. From 1.001ms, when the step rise ends, you linearly interpolate 4900 samples at 10µs intervals. The maximum amount by which it exceeds 1V on this grid is overshoot_v. You find the last sample outside 0.98 to 1.02V and record the time of the next sample as a time relative to the completion of the rise.

If you pick the time it first passed 1V, you miss ringing that goes out of band again later. If even the last sample is outside, settled_at_s is null, and if all samples are inside, it is 0. The boundary of the 2% band is included. The observation continues only up to the absolute time of 49.991ms, so this report is settling within that finite observation interval and the 10µs grid. It is not a proof of being stable forever after that or a certification of the continuous-time maximum.

You run the circuit calculation with maximum time steps of 5µs and 2.5µs respectively. You check whether the maximum difference of the two results at the same 10µs observation times is 10µV or less. The AC transfer function is compared with the analytical model as a complex number at all 241 points and the two required frequency points. A circuit with only the amplitude right and the phase wrong is rejected by this check. Convergence, model agreement, and the design requirement must all be satisfied to put it in the final candidates.

What it looks like in the field

Automation in an analog validation role is not just work of drawing numbers prettily. You must be able to find again which inputs you put in, what the real circuit was, and what margin there was against which item of the specification. If you keep the AC results and the transient response together, you can also explain how a noise-removal filter reacts to abrupt changes in a normal signal.

We connected the Python automation, basic analog quantities, validation planning, and data analysis requirements we checked in NXP's analog validation role posting to this task's file handling and condition judgment. This lab does not replace real instrument operation or real-hardware verification across temperature and process.

What you will do in the next lab

You write 8 steps: configuration validation → reading complex AC files → Bode numbers → transfer function → step observation → overall requirement judgment → file analysis → comparison CLI. At the end, you report the reason for your choice while keeping the original netlists, settings, logs, AC files, and step files as they are. Instead of deleting failing conditions to make a final candidate, leave the reason each was dropped from the candidates in each field.