That One Line — The Device Is Not Responding

In one line

I2C can only pull the line down. Raising it is done by a resistor, and that is why half of the faults are on the rising edge.

Why this was needed

A temperature sensor that was readable until yesterday is not readable today. The driver says only "the device is not responding". This sentence lumps together several causes — the address may be wrong, the sensor may be dead, the power may not be on, or the whole bus may be locked up. On the waveform, these four look completely different.

If you can read I2C, you can turn the driver's one-line error into what happened at which bit. That is the purpose of this module.

How it works

There are two wires. SCL is the clock and SDA is the data, and both are open drain. A device can only attach the line to ground with a transistor, and when it lets go, the pull-up resistor pulls it up to the supply. So falling is fast, and rising is slow at a speed set by the resistance and the parasitic capacitance. TI's I2C guides explain this asymmetry first with a figure — a small resistance makes communication fast but uses more current, and a large one makes it slow (SBAA565, SLVA704).

The rules boil down to two lines. Data changes only while SCL is low. And if SDA moves while SCL is high, that is not data but a condition. Falling is START and rising is STOP. NXP's specification states this definition as is (UM10204).

      START                                   STOP
SDA  ‾‾\____  A6 A5 A4 A3 A2 A1 A0 R/W ACK  ____/‾‾
SCL  ‾‾‾‾\__/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\__/‾‾‾‾

After START come the 7-bit address and one read/write bit, and the ninth bit is the ACK. At this position the master lets go of SDA, and the device whose address matches pulls it down instead. If no one pulls it down, it stays high because of the pull-up, and that is a NACK. That is, a NACK is not a signal a device sent but the fact that nothing happened. This is why the waveforms are identical when you point at the wrong address and when the sensor has no power.

A read transfer usually starts twice. First it passes the register number with the write address, then without a STOP it issues a repeated START and specifies the address again with the read address. If you issued a STOP in between, another master could cut in, so a repeated START is a declaration that "it is not over yet". And the master deliberately issues a NACK on the last byte to be received. This is not an error but means "stop sending". It is common to report the final NACK as a fault just from looking at the waveform.

Clock stretching is when a slave holds SCL and does not let go. It means "I'm not ready, so wait", and the master must wait until SCL is released. On the waveform it appears as one interval whose length is clearly different from the other low intervals the master made. In this course's capture, the median of the low intervals is 5 µs, but only one of them is 47 µs. When looking for the cause, the key is to ask "who made this interval" — a master cannot explain an interval it did not make.

The last is the weak pull-up. If the resistance is too large or the wiring capacitance is too large, the rise time gets long, and it cannot rise to VIH within the bit time. In this course's capture, SDA's 10 % → 90 % rise is 5.25 µs while SCL's is 1.00 µs. At 400 kHz the high interval of SCL is shorter than that, so SDA has no time to carry a 1. If you read at half voltage (1.65 V), the data looks fine, but if you read at 0.7 × 3.3 = 2.31 V, only one of the 18 intervals reads as a 1. Same file, different threshold, different conclusion.

What it looks like in the field

There is an accident in which the bus locks up. If the master restarts while the slave is sending a byte, the slave stops at the position where it was driving a 0 and does not let go of SDA. The master tries to make a STOP, but a STOP is formed by raising SDA, so it cannot. On the waveform there is a START but no STOP, and SDA stays low for a long time. A reboot does not clear it; you have to wiggle SCL a few times to make the slave send out the remaining bits.

You also see cases where pull-up resistors were placed on several boards and, combined, became too small. Then the rise is faster so communication works, but the supply current increases, and it comes to light late in a battery-life report. The rise time is not a value that is bad in only one direction.

What to check in the next quiz

It asks about the definitions of START and STOP, what actually happens at the ACK position, why a NACK on the last byte is normal, how to pick out clock stretching on the waveform, and which edge a weak pull-up shows up on.